The practical way to proceed is to let V GG = 0 V. It is not possible to solve for R 1 and R 2. Suppose now that Equation (62) results in a V GG that has the opposite polarity of V DD. These resistor values are selected by finding the value of R G from the current-gain equation or from the input resistance. We now solve for R 1 and R 2 assuming that the V GG found has the same polarity as V DD. Otherwise, V GG will have the opposite polarity from V DD, which is not possible according to Equation (62). Thus the term I DQR S must be greater than V GSQ in magnitude. The voltage, V GS, is of opposite polarity from V DD. We begin by rewriting the KVL equation for the gate-source loop. With R D and R S known, we need only find R 1 and R 2. Now that R D is known, we solve for R S using Equation (59), the drain-to-source loop equation. If the positive solution yields R D < K 1, we can proceed. If the positive solution results in R D > K 1, thus implying a negative R S, a new Q-point must be selected (i.e., restart the design). Solving for R D results in a quadratic equation having two solutions, one negative and one positive. The resistance, R D, is the only unknown in this equation. Solving for the sum of the two resistors yields We begin by writing the dc KVL equation around the drain-source loop, Since there are two unknowns, we require two independent equations. We now solve for the two resistors in the output loop, R S and R D. Refer to the curves of Figure 40(b) for an example. This procedure assumes that a device has been selected and that its characteristics are known.įirst, select a Q-point in the saturation region of the FET characteristic curves. Refer to Figure 40 as you follow the steps in the procedure. The designer’s job is to select the resistance values R 1, R 2, R D, and R S. The supply voltage, load resistance, voltage gain and input resistance (or current gain) are usually specified. You will not simply apply the approaches others have already done for you.Īmplifiers are designed to meet gain requirements assuming the desired specifications are within the range of the transistor. Reducing theory to an organized approach is what you will be doing.
As an engineer, you are seeking to do things that are not routine. If all you do to design a CS amplifier is to thoughtlessly “plug in” to the steps we present, you are missing the whole point of this discussion. Reduce design to a very routine process, you must convince yourself that you understand the origin of each step since several variations may be subsequently required.
We shall reduce JFET and the depletion MOSFET amplifier design to an organized procedure. The design procedure of a CS amplifier is presented in this section. The additional constraints are established to meet certain overall objectives (e.g., minimum cost, less variation in performance due to parameter changes). As in most electronics design, the number of equations will be less than the number of unknowns. We will attempt to define the unknowns in the design problem, and then develop equations for solving for these unknowns. We now explore the extension of the FET amplifier analysis presented earlier in this chapter to the design of FET amplifiers.
0 kommentar(er)
